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Objective: To design a 1.2V low-area low-power ADC for novel wide-DR CMOS image sensor in TSMC 130nm.
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Completed literature review and modelled 1st order Δ-Σ architecture in MATLAB Simulink to analyze analog modulator and digital filter trade-offs and sub-block specs
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Designed all analog ADC sub-blocks in Virtuoso such as Gm-C transconductor, high-speed comparator, current-steering DAC, and a voltage reference
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Converted single-ended voltage summation Δ-Σ architecture (first design iteration) to differential current summation architecture (final design iteration)
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Optimized modulator sampling rate and power consumption, analog layout area and modulator SNDR
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Led the analog design team consisting of two layout team members and coordinated analog-digital integration efforts with three digital design team members. Also worked with a graduate student (Devin Atkin) for integration of novel image sensor, chip floorplan and tape-out
Analog Modulator Sub-block: The Gm-C transconductor

Analog Modulator Sub-block: High-Speed Fully-Differential Clocked Comparator

Analog Modulator Sub-block: Current-Steering DAC

Analog Modulator Sub-block: Voltage Reference

Delta-Sigma Modulator Sanity Check

Analog Modulator Optimization Plots





Delta-Sigma ADC Output (Digital codes converted back to analog using MATLAB)



Modulator Sub-block Layout: Comparator

Modulator Sub-block Layout: Gm-C Transconductor

Modulator Sub-block Layout: Voltage Reference

Modulator Sub-block Layout: Current-Steering DAC
