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A 1MS/s, 8.33-bit ENOB Low-Area CT Δ-Σ ADC for CMOS Image Sensors 

  • Objective: To design a 1.2V low-area low-power ADC for novel wide-DR CMOS image sensor in TSMC 130nm. 

  • Completed literature review and modelled 1st order Δ-Σ architecture in MATLAB Simulink to analyze analog modulator and digital filter trade-offs and sub-block specs

  • Designed all analog ADC sub-blocks in Virtuoso such as Gm-C transconductor, high-speed comparator, current-steering DAC, and a voltage reference

  • Converted single-ended voltage summation Δ-Σ architecture (first design iteration) to differential current summation architecture (final design iteration)

  • Optimized modulator sampling rate and power consumption, analog layout area and modulator SNDR

  • Led the analog design team consisting of two layout team members and coordinated analog-digital integration efforts with three digital design team members. Also worked with a graduate student (Devin Atkin) for integration of novel image sensor, chip floorplan and tape-out

Analog Modulator Sub-block: The Gm-C transconductor


Analog Modulator Sub-block: High-Speed Fully-Differential Clocked Comparator


Analog Modulator Sub-block: Current-Steering DAC


Analog Modulator Sub-block: Voltage Reference


Delta-Sigma Modulator Sanity Check

Screen Shot 2022-07-24 at 9.30.37 PM.png

Analog Modulator Optimization Plots


Delta-Sigma ADC Output (Digital codes converted back to analog using MATLAB)

ADC Output Recreated.png
Recreated Output FFT.png
ADC Linearity.png

Modulator Sub-block Layout: Comparator

Comparator layout.png

Modulator Sub-block Layout: Gm-C Transconductor

Transconductor layout.png

Modulator Sub-block Layout: Voltage Reference

Voltage bias layout.png

Modulator Sub-block Layout: Current-Steering DAC

IDAC layout.png

ADC Achieved Specifications

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