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System-Level Modelling of a 200KHz Bandwith, sub-8mW, 5-9GHz Type-II RPLL in MATLAB Simulink

PLL Simulink Model

Tabulation of PLL Design Values

 Type-II PLL Open Loop Response (Hand Analysis)

Open Loop Gain.png

 Type-II Closed Loop Response (Hand Analysis)

Closed Loop Gain Pg1.png
Closed Loop Gain Pg2.png

PLL Locking Simulation (VCO Control Voltage vs Time)

Initial PLL Lock.png

 PFD "UP" Output Before Lock (Top) And After Lock (Below)

PFD Output UP.png

 Charge Pump Output Before Lock (Top) And After Lock (Below)

Charge Pump Output.png
Charge Pump Output.png

VCO Control Voltage Before Lock (Top) And After Lock (Below)

VCO Control Voltage.png
VCO Control Voltage.png

PLL Re-Locking Simulation (REF freq changed by +0.1%)

Changing Ref CLK.png

Static Phase Error After Lock

Phase Error After Lock.png
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