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A <6mV Error, 74.2 degrees Phase Margin Current Mirror Op-Amp in 45nm CMOS 

Current Mirror Op-Amp Open-Loop Schematic

Q1_testbench_DCOperatingPoints_only.png

AC Gain and Phase (TT corner)

Q1_Phase_Margin_TT.png

AC Gain and Phase (FF corner)

Q1_Phase_Margin_FF.png

AC Gain and Phase (SS corner)

Q1_Phase_Margin_SS.png

Voltage Error @ 1MHz (TT Corner) 

Q1_1MHz_transient_TT.png

Voltage Error @ 1MHz (FF Corner) 

Q1_1MHz_transient_FF.png

Voltage Error @ 1MHz (SS Corner) 

Q1_1MHz_transient_SS.png

Voltage Error @ 100MHz (TT Corner) 

Q1_100MHz_transient_TT2.png

Voltage Error @ 100MHz (FF Corner) 

Q1_100MHz_transient_FF2.png

Voltage Error @ 100MHz (SS Corner) 

Q1_100MHz_transient_SS2.png

Current Mirror Op-Amp Noise Hand Analysis

Noise Analysis Page5.png
Noise Analysis Page1.png
Noise Analysis Page2.png
Noise Analysis Page3.png
Noise Analysis Page4.png

Input-Referred Noise

Q1_input_referred_noise.png

Noise Summary @ 1KHz

noise_contribution_at_1KHz.png

Noise Summary @ 100MHz

noise_contribution_at_100MHz.png

Project Documentation (button below) includes:
1. Current Mirror Op-Amp Schematics with DC Operating Points, Component Parameters
2. Detailed Design Procedure
3. AC Gain and Phase across TT,FF,SS corner

4. Voltage Error across TT,FF,SS corner

5. Hand-analysis of Noise at 1KHz, 100MHz

6. Cadence Noise Analysis at 1KHz, 100MHz

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