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A 1.2pJ/bit PCIe Gen 5 Compliant 32Gb/s NRZ Transmitter In TSMC 16nm FinFET

TX System Diagram

TX_architecture.png

2:1 AMUX Schematic

AMUX_scm_v1.png

3-tap FFE Schematic

FFE_scm_v1.png

High-Swing CML Driver Schematic

DRV_scm_v1.png

16nm FinFET Technology Characterization

tech_char_v2.png

Channel Characterization

Channel_S11_S21_v4 copy.png

Transmitter Plots

TX Driver Bandwidth and Matching

Driver_S21_S22_v2.png

FFE + TX Driver PCIe Gen5 Compliance

P7_FFE_drv_out_v1 copy.png

32Gb/s FFE Output Eye Diagram (P7 Preset)

P7_FFE_output_v2.png

32Gb/s TX Driver Output Eye Diagram (P7 Preset)

P7_Driver_output_v3.png

32Gb/s RX Input Eye Diagram (P7 Preset)

P7_RX_input_v4.png

RX Input Bathtub Plot

P7_RX_input_bathtub_v1 copy.png

RX Input Histogram

P7_RX_input_histogram_v4 copy.png

Full Transmitter Timing Diagram

Timing_diagram_v2.png
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