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An 83.7degrees Phase Margin, 34.5MHz GBWP, 30.3V/us Slew Rate Two-Stage Op-Amp driving 50fF Load Capacitor in 45nm CMOS 

Two Stage Op-Amp Open-Loop Schematic

Q2_OL_testbench.png

AC Gain and Phase

Bode Plot.png

Slew Rate Testbench

Q2_SR_testbench.png

Rising Slew Rate 

Rising_Slew_Rate.png

Falling Slew Rate

Falling_Slew_Rate.png

Project Report (button below) includes:
1. Two-Stage Op-Amp Schematics with DC Operating Points, Component Parameters
2. Main VCO Op-Amp Specifications 
3. Detailed Design Procedure

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