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A Low-Power 10GHz LC VCO With Digitally Assisted Tuning for High-Speed Wireline Transceivers

  • Objective: To design a low-phase noise and wide tuning-range VCO for 10-25Gbps Serdes links in TSMC 130nm. View detailed project report

  • Compared ring, Colpitts and differential LC Cross-Coupled oscillator topologies

  • Analyzed and optimized a variety of design aspects of LC-VCO such as cyclo-stationary and tail PN, output voltage swing, gain, tuning range, power consumption, parasitics, effects of lossy varactors and inductor Q

  • Added distributed switched capacitors to VCO architecture for wider tuning range and studied impacts of additional device parasitics.

  • Prepared performance comparison with other published works and presented the design to course instructor , Dr. Leonid Belostotski

VCO Core With Tail Current Source

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Q of the chosen inductor

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Differential Pk-Pk Swing of VCO Output (without buffer loading)

Screen Shot 2022-07-24 at 11.11.47 PM.png

VCO Phase Noise (with current-mirror as tail current source)

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VCO Frequency Spectrum at 10.6GHz (PSS Analysis)

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Addition of Distributed Capacitors to VCO Core for Wider Tuning Range

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Overall VCO architecture with 10 distributed capacitors

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VCO Tuning Range Characterization

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Performance Comparison With Previous Works

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