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A Low-Power 10GHz LC VCO With Digitally Assisted Tuning for High-Speed Wireline Transceivers
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Objective: To design a low-phase noise and wide tuning-range VCO for 10-25Gbps Serdes links in TSMC 130nm. View detailed project report
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Compared ring, Colpitts and differential LC Cross-Coupled oscillator topologies
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Analyzed and optimized a variety of design aspects of LC-VCO such as cyclo-stationary and tail PN, output voltage swing, gain, tuning range, power consumption, parasitics, effects of lossy varactors and inductor Q
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Added distributed switched capacitors to VCO architecture for wider tuning range and studied impacts of additional device parasitics.
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Prepared performance comparison with other published works and presented the design to course instructor , Dr. Leonid Belostotski
VCO Core With Tail Current Source

Q of the chosen inductor

Differential Pk-Pk Swing of VCO Output (without buffer loading)

VCO Phase Noise (with current-mirror as tail current source)

VCO Frequency Spectrum at 10.6GHz (PSS Analysis)

Addition of Distributed Capacitors to VCO Core for Wider Tuning Range

Overall VCO architecture with 10 distributed capacitors

VCO Tuning Range Characterization

Performance Comparison With Previous Works
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